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Wednesday, May 18, 2011

FPGA-based Form Factor Serves Radar ADC Needs

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FPGA-based Form Factor Serves Radar ADC Needs

Advances in ADCs, combined with larger, more powerful FPGAs and the new open standard FMC format, are fueling improvements in radar systems.
JEREMY BANKS, CURTISS-WRIGHT CONTROLS EMBEDDED COMPUTING
 

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In Electronic Warfare (EW) the difference between life and death can come down to just a few radar pulses. There’s a matter of milliseconds in which a ship’s countermeasure system can sense an oncoming missile threat. Radar signals from that threat won’t even show up until it’s as near as 10 km from target. Once identified the ship’s fire control system can send out a deceptive signal about its position before the enemy weapon has a chance to lock onto the ship’s radar, safely diverting the course of the speeding missile. This makes it critical to improve the speed and resolution at which embedded signal intelligence systems can take incoming analog sensor data and digitally convert it so that it can be processed in a useful way. An example system along those lines is Raytheon’s Phalanx Close-In Weapon System (Figure 1).
Figure 1
Raytheon’s Phalanx Close-In Weapon System is a rapid-fire, computer-controlled, radar-guided gun system designed to defeat anti-ship missiles and other close-in air and surface threats assessment.
The good news is that the newest generation of commercial ADCs, combined with larger, more powerful FPGAs and the new open standard FPGA Mezzanine Card (FMC), can now significantly improve these EW systems through the direct digital conversion of the analog signal, eliminating the need for an intermediary down conversion stage. The resulting performance benefits are helping to change the COTS receiver industry landscape. 
Pushing the ADC Boundaries
Today’s highest end ADCs, with greater bandwidth and higher resolution than previously available, are increasingly being used in demanding military applications to provide direct digital sampling of wideband Receiver Intermediate Frequency (IF) analog sensor data. This results in improved performance and lower costs by eliminating the need for a heterodyne receiver down conversion stage in the system. 
Previous generations of ADC conversion technology have not had the speed or resolution at the required frequencies to function as a true RF front end without down conversion. Today’s newer devices, however, feature multi-Gigasample per second (Gsample/s) converters in both directions with the high resolution needed to directly connect to the RF front end in close proximity to the antenna system. This new capability is fueling increased direct (baseband) conversion.
As recently as two or three years ago, leading off-the-shelf high-end ADCs could only achieve 1.5 to 3 Gbit/s bandwidth performance with 8-bit resolution. Since then, the performance of commercial ADC devices has increased dramatically. Today’s high-end ADCs are approaching 4G sample/s bandwidth with 12-bit resolution. Earlier ADC technology either wasn’t fast enough, or lacked the resolution or the combination of the two to enable direct digital conversion of analog signals. This resulted in more cost and reduced performance because a system would typically require two RF heterodyne receiver front-ends to handle the down conversion stage before the data would get to the ADCs attached to the FPGAs. Today’s FPGAs function as true processors that have large blocks of digital circuitry in which signal processing algorithms such as FFTs can be stored. FPGAs are very good at handling signal processing in the digital domain.
Today’s faster, higher resolution ADCs have the ability to take an input signal at a microwave frequency and convert it at that frequency rather than requiring the use of a costly intermediary down converter. Higher-end ADCs can sample at rates in excess of 3 to 4 Gsamples/s, which approaches the 1.5 GHz L-Band and beyond. Sampling rates that exceed 1 GHz and faster now allow bandwidths of up to 500 MHz to be processed. And the higher bit resolution of the new ADCs has increased system dynamic range, the span from the weakest to the strongest detectable signal that it can handle. 
Today’s high-resolution ADCs can sample at rates near 200 Msamples/s, and soon will reach 250 Msamples/s with 16-bit resolution. They can dramatically enhance the capabilities of wideband receivers by increasing their sensitivity and selectivity, which affects the system’s ability to intercept and characterize captured signals.
FPGAs Make it Possible
The design challenge at these high data rates is how to interface these newly obtainable levels of resolution to the digital domain, a task that traditional processors can’t handle. The answer is a combination of baseboard FPGAs and FMC I/O cards. When combined with larger FPGAs and the new industry standard FMCs, the new generation of ADCs is enabling system designers to integrate open standards-based board systems in which both ADC and DAC capabilities are directly coupled to the processing element, provided by the FPGA. The result is an order of magnitude improvement in latency from input to output. Even better for Space, Weight and Power (SWaP)-constrained embedded systems, the increased bandwidth of the new ADC devices does not come at the cost of a comparable rise in power consumption. We are seeing these devices with power dissipation rated near 2W per converter, which means that a quad-channel FMC will require less than 10W. 
The FMC (VITA 57) standard, recently approved by ANSI, provides a method for directly coupling FPGAs on the baseboard with I/O devices on the small mezzanine FMC board. FMCs enable the board’s bus structure to be bypassed, providing direct I/O to the FPGA processing element on the host card. This drastically improves data rates and reduces latency compared to designs where the I/O devices reside on the main PCB. Another advantage is that FMCs make it easier to tune particular I/O needs with a common processing engine and to upgrade performance as newer and better I/O devices become available without a major baseboard redesign. 
Supporting High Data Rates
In comparison to FMC cards, standard I/O mezzanine cards, such as PMC and XMC, tend to support CPU-type buses such as PCI Express and PCI-X, for which data bandwidth is limited to 1 to 2 Gbytes/s. In a direct one-to-one connection, today’s FPGAs can support the very high data rates provided by the use of locating I/O on FMC cards, while eliminating the issue of latency resulting from the bus structure. Compared to XMC mezzanine cards, and depending on the devices used, FMCs can deliver an order of magnitude increase in bandwidth and similar reduction in latency. FMCs can support data throughput rates of 5 to 10 Gbytes/s, while XMC provides 500 Mbytes/s to 1 Gbyte/s. Key to the high speed of FMCs is the simplicity of their design: the FMC specification makes provision for a large number of parallel I/O connections, up to 160 single-ended (80 differential pair) signals, in addition to high-speed serial connections, directly connected to the FPGA(s) located on the base board. Figure 2 shows a side by side comparison between an XMC board and an FMC board.
Figure 2
FMCs (bottom) can support data throughput rates of 5 to 10 Gbytes/s, while XMC (top) provides 500 Mbytes/s to 1 Gbyte/s. The simple FMCs design also allows for a large number of parallel I/O connections.
Dual ADCs on FMC
An example of an FMC card designed for use with an FPGA host card such as the FPE320, is Curtiss-Wright Controls’ ADC511 Dual Channel Analog Input FMC, which features dual 400 Msample/s 14-bit Texas Instruments ADS5474 ADCs. Each of the module’s ADCs supports a sampling rate up to 400 Msamples/s, within an analog bandwidth of over 1.7 GHz, and provides 14-bits of digital output. By routing the ADC device interfaces directly to the FMC connector, the ADC511 enables an FPGA on the host board to directly control and receive data. A choice of sample clock sources is provided, including an onboard source that supports sampling rates of 300, 320 and 400 Msamples/s, as well as the ability to use an external sample clock. Input and output triggers are provided enabling the number of input channels to be increased by synchronizing multiple ADC511 modules.
Thanks to the new generations of ADC, FPGA and FMC products, we are seeing more and more applications in which direct conversion is occurring. For COTS signal processing system designers the trends are beneficial. Life-saving high-performance EW systems can be deployed faster and cheaper using commercial devices in designs that can flexibly be upgraded and modified using low-cost FMC mezzanine modules.
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